Comments by "Scott Franco" (@scottfranco1962) on "The Growing Semiconductor Design Problem" video.

Good overview. I left verification just after the Verilog revolution came to pass. We used hardware simulators at that point, with accelerated simulation. Sea-of-fpga emulation was not yet popular. The bottom line was that the company I worked for (nameless, but huge trust me) was new to hardware chip design. They had lots of money to buy toys, but had the idea that the tool would solve all. Thus the expectation was that the new, more expensive tool would relive them from the need to write test cases. I enjoyed being the one employee who understood the tools, but rapidly realized that it was a falling rock I had volunteered to sit under. I left the company soon after.
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@ttb1513 The last company I work at silicon design for, Seagate, was emblematic of the basic problems with ASICs. It was 1995 and they were new at ASIC design in house. And they weren't very good at it. It was random logic design before Verilog. An example of this was our timing verification. We had timing chains that were too long for the cycle time, and thus they simply alllowed for the fact that the signal would be sampled in the next clock cycle. Now if you were an ASIC designer back then, what I just said would have made you reach for the tums, if not a 911 call for cardiac arrest. Its an open invitation to metastability. And indeed, our AT&T fab guys were screaming at us to stop that. I got put in charge of hardware simulation for the design, and I have detailed this fiasco in these threads before, so won't go over it again. The bottom line was that ASIC process vendors were loosing trust in their customers to perform verification. The answer was that they included test chains in the designs that would automatically verify the designs at the silicon level. It mean that the silicon manufactured design would be verified, that is, defects on the chip would be verified regardless of what the design did. My boss, who with the freedom of time I can now certify was an idiot, was ecstatic over this new service. It was a gonna fixa all o' de problems don't ya know? I pointed out to him, pointlessly I might add, that our design could be total cow shit and still pass these tests with flying colors. It was like talking to a wall. In any case, the entire industry went that way. Designs are easier to verify now that the vast majority of designs are in Verilog. I moved on to software only, but I can happily say that there are some stunning software verification suites out there, and I am currently working on one, so here we are.
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