Comments by "OpenGL4ever" (@OpenGL4ever) on "Visual Electric" channel.

  1. This was a very interesting and great video. Thank you very much. But i have one questions. Your 3 code examples for Gate, Dataflow and Behavioral Level do produce the same end result, but does it also generate the same hardware inside the FPGA? I'm asking because I would like to know if the design was much more complex, e.g. a CPU implemented in an FPGA, would the CPUs of the 3 codying style variants be the same with the same performance? Or would it be possible, for example, that the dataflow level variant generates a faster CPU on the FGPA than a CPU based on the behavior level variant and vice versa?
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