Comments by "Mikko Rantalainen" (@MikkoRantalainen) on "Linus Torvalds: RISC-V Repeating the Mistakes of Its Predecessors" video.

  1. I interpreted that as doing the same mistakes for the kernel code (e.g. incorrect locking between threads for CPU native code), side-channel data leak vulnerabilities (Spectre-class vulnerabilities in hardware) and poor performance for TLB cache misses or the need to force clearing TLB cache. It would be great if RISC-V could avoid all those mistakes but I'm expecting them to hit at least some of them.
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