Comments by "Scott Franco" (@scottfranco1962) on "The Promise of Open Source Semiconductor Design Tools" video.

  1. I think these go in two different directions. The old flow is graphical floorplanning, cell based design, etc. The new way is Verilog, tested on FPGAs and sent off to a "conversion" firm or to the end fab that takes the design and runs it though automated floorplanning and process prep. All of the SOCs I have been involved with for the last 15-20 years have been done this way. The nice thing is the Verilog route is going to be much more amenable to open source processing.
    9