Comments by "Valen Ron" (@valenrn8657) on "The Evolution Of CPU Processing Power Part 2: Rise Of The x86" video.
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@nextlifeonearth
(D) concerning memory as the direct target of ALU instructions is the only aspect that's central to what distinguishes the x86 pseudo-RISC kernel from a true RISC kernel. If some person complaining about x86 doesn't mention this, his or her argument is half-baked. Here, again, Chris was not as forthcoming as he ought to have been. He actually comments on write ports to the register file as a pertinent modern design issue with complex trade-offs. x86 requires fewer write ports through its unique capacity to exploit the dcache as part of a (hugely) extended register file.
The rmw instruction family in x86 is a bit like zero page in 6502/6809, as both of these allow memory to substitute for registers you don't have at far less cost than you would otherwise experience. The rmw instructions form a computed address on the fly—without committing this to a named register—and then operate on the memory location (both a read and a write), also without committing this to a named register file. This is why the register colouring algorithm for the original x86 ever survived to live another day, despite the gross inadequacy of the named register file.
What does end up a bit stressed out in silicon is what the Pentium Pro used to call the MOB: memory order buffer. A lot more addresses need to be checked for ordering requirements (mostly use of overlapping memory addresses in close succession). I once read a discussion by a core member of the Athlon design team who said that this was almost a blessing in disguise. In a pure RISC design, you have to perform virtual address translation twice: once on read, again on write. In implicitly fused rmw on x86, you only need to perform virtual address translation once. And so the final score: a busier (and hotter) MOB, but a less busy (and less hot) TLB.
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