Comments by "bighand69" (@bighands69) on "New 2nm IBM's transistors explained" video.

@davidporterrealestate I do not think any of that is trade secrets but still putting the sons name up would be foolish.
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@earthengineer8344 The 2nm size is just a marketing gimmick as they are nowhere the size of a 2nm transistor size. The chip shortage is to do with the pandemic because it actually affected inventory systems on every aspect of manufacturing. It is not just the actual chip production that has been affected everything from water services, materials production, mining, transport and tool making has been in contraction. International markets are based on supply and demand and when that balance is interrupted and confidence is eroded it causes problems. There is shortages in everything from wood, food, minerals and so on.
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@earthengineer8344 Moore's law is about how many transistors can be placed in a particular area. People are implying that the transistors are 2nm and are under the impression that we now have reached the limit. You will routinely hear people talking about how Moore's law is finished and that the transistors cannot be made any smaller.
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@Gary Menezes They are nowhere near the size of 2nm transistors but the marketing makes people believe that they are. In theory that would mean that they would have 430 trillion transistors per square inch if they had 2nm transistors. At the moment they are lucky to have about 500 million per square inch. They are about 25 doubling cycles of those types of growth figures. Now I am being very conservative in regards to that.
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You do not think what is over? Moors law is not shrinking transistor sizes.
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Just to let people know the real transistor sizes are nowhere near the claimed 2 nm size. With that they could easily put 10 trillion transistors per square inch and with optimization they could go up to 500 trillion transistors per chip. I think people have got confused in thinking that Moore's law is about the size of the transistor and people right now think they have 2nm transistors and that the area that the integrated circuit exists on is packed right up to its maximum density. In reality there is still another 60 years of moore's law to play out and that is assuming that integrated circuits stick with 2d transistor layouts on the integrated circuit. 3d dimensional parallel integrated computation would change that entirely but we are not at that point yet.
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@imconsequetau5275 Moore's law is not broken and it is people's lack of understanding that is at stake here. The semiconductor industry has been on a marketing pathway for decades. They have sort of convinced people that Moore's law is to do with size of the transistors that they are marketing. Moore's law is about the number of transistors that can be put on an integrated circuits such as 1 square inch. Per square inch right now the number of operational transistors is about 500 million. And the doubling period of 18 months has held up. Not every company that is involved in this has kept up with that figure because it is not about companies keeping up but the level of growth of transistors per square inch in the industry as a whole. So what we really have is companies pretending that they on an individual level are somehow producing Moore's law level growth every 18 months. For them to keep this promise up they all would have to have completely new chip sets every 18 months that double in capacity.
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People are confused as Moore's law has nothing to do with transistor sizes and is an observation about how many transistors can be operated on an integrated circuit. And it does not matter if it is 18 months or 36 months. 2nm does not mean they have an integrated circuit where each transistor has a foot print of 2nm. That does not mean they have 10 trillion transistors per square inch. At this point they are lucky if they are near 500 million per square inch. They probably have another period of 30 doubling cycles before they reach the actual theoretical limits of space in terms of how many transistors they can squeeze onto an integrated circuit. And that does not take 3d stacking into account or other types of 3d architecture. Finding ways of dealing with impedance and leakage is really the challenges to be faced.
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