Comments by "Vitaly L" (@vitalyl1327) on "Can SRAM Keep Shrinking?" video.

  1. ​ @Fiercesoulking it is common to use 2x clock on SRAM blocks to simulate dual port access
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  2. as if SRAM is only cache. Every single register is, technically, SRAM. Every little table (all those reordering buffers in your OoO CPU cores and hundreds of other blocks).
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  3.  @deang5622  exactly, if we follow this logic we can remove the entire CPU, for example, and replace it with an equivalent bit-serial implementation in just a hundred transistors, that would do exactly the same work (but hundreds of times slower).
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