Comments by "Le YASEP" (@leyasep5919) on "The Promise of Open Source Semiconductor Design Tools" video.

Thanks for this video ! That subject is "my turf" and I've been invested in this field for more than 20 years !
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The open source crowd will take any and all paths toward getting to silicon ;-)
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@SianaGearz Furthermore, wiring capacitance and all other types of interferences will destroy the transition time.
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"open source hardware innovations like RISC-V" sorry but RISC-V is not innovation, it's more like standardisation on the least common denominator... it is a VERY polished RISC but brings close to nothing new to the table :-/
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@MostlyPennyCat You know you never stop to learn ! Have a look at the GHDL compiler, which enables things even the VHDL designers couldn't imagine (I have done actual real-time simulations based on the computer's clock, input-output to the printer port or the Linux Framebuffer...) VHDL takes time to get your head around but it's well worth it. GHDL changed the rules too. I do most of my EDA work with VHDL now, with a bit of bash scripting to glue it all. After you feel comfortable comes the real question : what do you want to do with this technology ?
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@dand337 more replies 🙂 > Is riscv modern enough isa to be realistically considered? modernity is not a criterion for adoption, there are more practical issues to solve before : is the platform widely adopted ? This means : how many people do use it, developing tools and enhancing them ? Is there some support or dynamic ? RISC-V is modular and adds extensions here and there and wherever they like or fancy. So there will be adaptation, though also some fragmentation because few chips can have all the extensions, creating a want for more features or a race to the latest feature level... such a race is a dynamic that the industry loves and there is little risk for them. Now adoption depends on the specific needs of each project. RISC-V is quite good for microcontrollers and can displace several ARM offerings but I believe it is a bit less efficient or compact because RISC-V tries to "be good enough at everything" but it can't perfectly match everything. > I mean chinese are literally copying mips with loongarch so ISA doesn't seem to be a very important factor. Some Chinese have adapted RISC-V to support more flexible addressing modes that are sorely lacking, due to the mantra of minimalism that reduces the ILP. Ideally this should be backported into the main ISA but I have no idea what's going on there, and there might be some "not invented here" syndrome, and/or philosophical fundamentalism, who knows, but the Chinese can adapt whatever they care to copy... I'm more interested at what they could invent from the ground up, if they ever dare. I don't know if I answered all your questions but that's quite some food for thought.
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they do not compare on the same basis. On one side you'll have all kind of close-to-nothing-to-pay software that is portable, scalable (you can run as many instances on any computer as you want), easy-to-hack, but low performance and low gate count. OTOH you have extremely expensive, hyper-featured, industry-proven, ultra-high-scale systems that you can only run on cherry-picked computers "if the SW provider agrees".
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@Asianometry heh, don't feel sorry for my nitpicking :) BTW check your inbox ;-)
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@MostlyPennyCat RISC-V is not as open as you seem to think. It's a standard for ISA that is controlled by a cartel of companies who pay for having first dibs on new extensions, and fight for imposing their own view by being "first to market". You are only free to follow, not innovate (because change will you make "incompatible"). Furthermore the architecture is polished but brings nothing to the table because it is based on a 40 years old architecture that has already been stretched to the extremes but there is nothing new, no real innovative concept that brings us to the 21th century. Only extension to the same old RISC-1 and MIPS concept and instruction format. The YASEP is another "free" ISA with features derived from 20 years of observing where other ISAs evolved and failed. It learned from the failure of the F-CPU project (started in 1998) and I develop yet another even simpler ISA right now. I can start from scratch and reconsider every single choice, but RISC-V has 4 decades of legacy... Feel free to contact me to discuss more about it.
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Hi @dand337 ! I'll try to reply objectively and usefully. > wasn't risc-v introduced to just drop this baggage? As far as I know, no. Look at the ISA closely then read the Patterson & Hennessy books : you'll find a very close match of the architecture.If you wanted to "drop baggage" you would diverge in a lot of details and structures. However RISC-V takes the best of MIPS, from their experience, and use all the capital of the existing architecutres to lower the bar of entry to the lowest possible, in order to let as many people in as possible. The original team did some research to circumvent or avoid patents, and there you go. > Do you think risc-v will be able tackle arm? Is risc-v better than arm? I think you all missed a little detail : no need to "tackle" ARM. First because ARM has already acknowledged the threat some years ago by creating a short-lived FUD website. But ARM is not the target and RISC-V has already killed its own father : MIPS is virtually no more. Patterson has "won" over the companies that have taken his baby away from him. ARM is quite different though. > What would you want to see in a new ISA then? More than the "bare minimum" of the base RISC-V ISA. RISC-V follows a loooong tradition of a certain way to design compilers and it's quite efficient, sure. But compilers have evolved since. But they retain the old structures of the old CPU architectures they try to serve... RISC-V is based on 40-years old paradigms that are so entrenched that there is no life possible outside of it. You can't compile C ? then you can't compile Linux, so you're dead before you start. And C has choked and undermined a LOT of the current SW industry. I believe that one specific trait of RISC-V/MIPS is the memory access mechanism. It's pretty good for single-issue microcontrollers (or R2000 or R3000 CPUs of the 80s) but it doesn't scale. Superscalar and out-of-order struggles with the load and store instructions.
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@yxyk-fr apparently my answers don't get published 😕
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