Comments by "Anders Juel Jensen" (@andersjjensen) on "Asianometry"
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Nice episode John :) I'm totally hooked on your deep dive into semi conducter manufacturing, so please, by all means, go on and explore every little nook and cranny. Methods, techniques, history of development, supply chain, global impact, etc, etc. It's all ace, as you're good at structuring an interesting narrative and delivering with impeccable pacing. 10/10.
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I'm not a financial advisor, but the reason that TSMC isn't crazy over valued like some other tech companies is probably that they're enormously predictable in their future income. They book wafer agreements 3-5 years in advance, build fabs that can fulfill that demand and then run them at ever lower margins until they're "worn out". This means they can't suddenly invent a hot new thing and become the latest fad overnight. But they have consistently delivered on their profit projections, and since they produce for every player in the AI space (Even Intel is using them for their NPUs, instead of using their own fabs for that), Apple, a hefty portion of the Android phone market, and most the PC space in general, I think you could do worse than buy TSMC stock. That is, if you buy stocks to generate passive income. If you buy stocks in the hope they'll gain value, so you can sell them for a profit, then TSMC is probably not the best bet.
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You're right, but the way you worded the second part it becomes hard for laymen to understand that when you say "charges" you're not referring the act of "charging up the battery" but rather referring to "the amount of Coulombs".
So for anyone curious:
Watt (rate of electricity consumption) = Joules/second ("energy chucks per time unit")
Watthours (total electricity consumption) = Joules/second * 3600 seconds (so the seconds cancel out and you're left with 3600 Joules)
However, Watt is also equal to Volts * Amps (sorry physics teachers for the laymanified notation).
This means that when you have a, say, 3.7V battery rated for 1000mAh of capacity you just multiply the two to get it in mWh, which in this case is 3,700mWh. Then divide by 1000 to remove the "milli" part and you're left with 3.7Wh, or divide by 1000 again to get to the kWh you're used to from your electric bill. In this case 0.0037kWh.
But here's the catch: What I just said is complete nonsense... Because a battery does not deliver it's rated voltage from 100% to 0% capacity. The voltage will decline as the battery discharges. This means that you will, in fact, not get 3.7Wh our of the example above. The battery will start at 3.7V but end at around 2.2V (I'm using my Vape battery as an example) before it's sufficiently "flat" to not be able to drive my "device".
And that's the reason why battery capacity is measured in amp-hours (or milliamp-hours for small stuff), as the Watt-hour approach "is bogus" despite it looking more familiar.
You can, however, go V * mAh * 3/4 and get a reasonable approximation for modern lithium batteries. "The constant" will change depending on the battery technology, but I've rambled on for long enough, so I'll spare you all for a lecture on the implications of a battery's internal resistance and how that directly relates to Ohm's Law.
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@chrimony If a 66MHz CPU has an IPC (provided no memory bottle neck) which is 15x higher than that of the 1GHz, then they have performance parity.
The Athlon XP 1500+ (1.3GHz) has a single threaded PassMark score of 251. The Ryzen 7 7800X3D (5GHz) has a single threaded score of 3757. Adjusted for clock speed advantage that's a score of 977 which means it has an IPC that is ~3.89x higher. Which is kinda funny, because it has a clock speed advantage factor of 3.85x. So if we aren't too pedantic we can say "Half the performance uplift is from clock speed and half is from IPC gains.
In the ~15 years between them the ~15x total single threaded performance uplift doesn't track Moore's Law, but one is a single core, the other is an 8 core. For tasks that scale linearly with cores that's a 120x performance uplift which is pretty damn close to the 128x Moore's Law projected.... But the current line of AMD Ryzen goes up to 16 cores, so there is that.
TL;DR: While clock speeds only gain 10-15% per node generation these days, the ~70% shrink each generation is gaining more and more on the clock speed in terms of generational gain. If we do this comparison again in 10 years 1/3 of the performance will be from clock speed and 2/3rds will be from IPC (it already is if we compare to a 1999/2000 era CPU, but I didn't have a verifiable online source handy for you).
So I stand by the statement. Yes, it's an over simplification, but to understand CPU progress it's a vital concept to understand. "IPC, over time, is everything".
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@ryandarrah4247
1) Intel and Samsung uses the precise same machines from ASML, but cant reach good yields at the feature sizes TSMC has been churning out on mass production nodes lately.
2) Logic design is completely decoupled from manufacturing. Both AMD, Nvidia and Intel (yes, Intel) uses TSMC for manufacturing. AMD and Nvidia are on the leading nodes because they need the best. Intel uses TSMC legacy nodes (for chipsets, auxiliary devices, network chips, etc) because that's cheaper than keeping their own old plants running.
3) EUV technology is not "an American license" without stretching the meaning of that word into oblivion. ASML was part of the EUV research conglomerate right from the get-go, along with a number of other companies. Every member got a full non-revocable license, but not the right to sub-license the technology, because the research expenses were (partly) subsidised by US government funds.
But all of that is splitting hairs/muddying the waters... because my original statement wasn't about research or making process equipment. My original statement was about manufacturing which Taiwan, currently, is the champions of, to such a degree that both the US and the EU are starting to worry (Hence the US passed The Chips Act, and the EU is doing similarly).
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@aekue6491 I work for a sub contractor for a big international defence contractor. We have long since been briefed that porting existing GAA designs to BPD-GAA will be, and I quote, "a largely automated process for embedded memory and gate logic, but will require substantial consideration and planning ahead of time for analog circuits".
Since we work almost exclusively in the boundary layer between analog and digital (such is the nature of real-time signal analysis and shaping) we are currently "a little bit freaked out" as we are in mid-stage design of a GAA based solution that would ideally be finalised and rolled out as BPD-GAA, as that offers vastly superior noise characteristics. However, we are only now starting to get the builtin points on what to account for early to facilitate a reasonably straight forward porting process.
Everything is still tightly under NDA from "the big three" but from the gossip I hear the situation is largely identical everywhere: The EDA tools will a breeze for the logic folks (CPUs, GPUs, accelerators, PLCs, FPGAs, etc, etc) but us analog folks (memory controllers, radio spectrum technologies, PCIe/CXL, optic signal modulation, etc, etc) will be the whipping boys as usual. We generally only get good EDA automation and integration of a node once it is no longer relevant for us (aka, once it's mature and cheap enough to make bulk crap products on like wireless doorbells and fridges and what have you).
I hope that satisfies your curiosity, as I can't really divulge anything that is more specific than this.
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