Comments by "Anders Juel Jensen" (@andersjjensen) on "How TSMC Keeps Getting Better" video.

  1. Last I heard TSMC is introducing N3E which is "only" a 60% density shrink as opposed to the standard 70%, but it's already yield ramping right. This shouldn't be a big issue since N5 was already a bigger leap over N7 than normal. 84% in the best cases actually. So from N7 to N3, on average, follows the 70% density shrink every two years.
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  2.  @SianaGearz  The advantage of smaller transistors is faster switching time (higher frequency chips) and faster signalling between each transistor (signals propagate at the speed of light). The first disadvantage is greater leakage (wasted power), but this is partly offset by the better voltage/frequency curve. That is to say: if we only "harvest" some of the frequency gain in exchange for lower operating voltage it's still a net gain. The power density problem is not inherent to node shrinks. It's inherent to competition. Laptop chips run at 15W and get like 80% the performance of their 65W desktop cousins. We still make chips about the same size all the time, so the cooling area remains much the same. We just cram more transistors (which each use less power) into the same size package for a net performance gain.
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  3.  @_TeXoN_  Electromagnetic signals travel at the speed of light in the medium they travel in. Just like light travels through air.. at the speed of light in air. We generally don't bother to distinguish between "the speed of light in a perfect vacuum", which is what think of when saying "the speed of light", and "the speed of light in this particular alloy" because in microprocessors (and other high quality electronics) it is at 95-99% the speed of light in a vacuum. Frequency scaling still happens despite you not seeing much of it in modern processors. This is because it is difficult to retain good IPC (Instructions Per Clock) at higher frequencies on the rather complex instruction sets of PCs. Every time TSMC markets a new node you'll see them state something like "20% more speed at ISO power or 40% power reduction at ISO speed" (those happen to be the numbers for N5 over N7). The chip designer can then mix and match between those two extremes to suit their needs the best. ASICs (that is, logic chips that don't interpret programs because they ARE "the program") see perfectly good frequency scaling if designed right.
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