Comments by "Anders Juel Jensen" (@andersjjensen) on "Semiconductor Immersion Lithography" video.

  1. TSMC N5 and N4 are not even fully EUV. Almost only the fins in the FinFETs are made with EUV. All the TSVs and most the routing layers are made with 193i. And the reason is simple: The wafer throughput is much much higher on 193i. So if a chip has 80 layers and only 5 of them are EUV and the rest are 193i you need, say, 1 EUV machine and 8 193i machines for the same throughput as 25 EUV machines would give you. Considering just how brutally more expensive the EUV machines are this is the difference of having a break-even after 3 years at full capacity or 30 years at full capacity.
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  2. They can. And some of the patents are starting to expire. But they lack the practical knowhow (a patent is practically useless other than telling you where to start looking), so yeah, 10 years sounds about right.
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