Comments by "Lepi Doptera" (@lepidoptera9337) on "arrays are weird" video.
-
The linker will tell you. It's a bit more complicated than that, of course, because not every program on a multi-tasking machine can have the same memory sections mapped to the same hardware address, so what the linker actually tells you is a symbolic address that merely points to the entry in the memory management unit, which then translates that to the physical hardware address that the CPU puts onto the address bus. Even that is a multi-stage process on modern CPUs because the L1 and L2 caches are still between your program and the actual memory. So instead of grabbing the data from the main memory, the machine will try to get it from L1 first, if that fails from L2 and if that fails it will reload the caches from the main memory. Word to the wise: you really, really, really don't want that to happen because your 5.3GHz racer then basically falls back to the speed of an 80 MHz CPU or so... because the CAS latency on DDR4 is still on the order of 12.5ns! I used to have faster (but much, much smaller) memory than that on one of my boards in 1995... so we have been basically standing still with regards to board level memory access times for like 30 years now. Chip level memory is orders of magnitude faster now, of course, so try to write your program in such a way that it doesn't jump around in memory too much so that the multi-level caching strategy can actually perform its miracles.
2
-
1
-
1
-
1
-
1